Radiation hardness testing determines the effect of neutron radiation on materials, components, and instruments. This procedure is also used to harden components for use in applications where they may be exposed to neutrons. Applications include aerospace, defense industries, telecommunications, and electronics. Depending on the application specimen can be irradiated with fast (high energy) neutrons, thermal neutrons or the unperturbed neutron energy spectrum. Note that the NIF position can be configured to operate with energized electronics for real-time data acquisition or other purposes. The NIF and NTD positions are maintained close to ambient temperatures (30 C +/- 5C). While the CIF and PTS can reach 200-300 C depending on the specifics of the experiment. Fast neutron dose is measured in accordance with ASTM E265-15. Irradiations can be performed in accordance with ASTM F1190-11, MIL-STD-883, and MIL-STD-750.
Radiation effects on electronics are normally divided into the following categories according to their effect on the electronic components:
Total ionizing dose (TID)
Total Ionizing Dose effects on modern integrated circuits cause the threshold voltage of MOS transistors to change because of trapped charges in the silicon dioxide gate insulator. For sub-micron devices these trapped charges can potentially "escape" by tunneling effects. Leakage currents are also generated at the edge of (N)MOS transistors and potentially between neighbor N-type diffusions. Commercial digital CMOS processes can normally stand a few Krad without a significant increase in power consumption. Modern sub-micron technologies tend to be more resistant to total dose effects than older technologies (in some cases up to several hundred Krad). High performance analog devices (e.g. amplifiers, ADC, DAC) may though potentially be affected at quite low doses. Fast neutron irradiations of this type can be performed at MNRC. Gamma-ray irradiations of this type can be conducted at an associated private laboratory.
Hadrons may displace atoms (therefore called displacement effect) in the silicon lattice of active devices and thereby affect their function. Bipolar devices and especially optical devices (e.g. Lasers, LEDs, Optical receivers, Opto-couplers) may be very sensitive to this effect. CMOS integrated circuits are normally not considered to suffer degradation by displacement damage. The total effect of different types of hadrons at different energies are normalized to 1 Mev Neutrons using the NIEL (Non Ionizing Energy Loss) equivalent. Irradiations of this type are conducted in the NIF irradiation position.
Single event effects (SEE)
Single Event Effects refer to the fact that it is not a cumulative effect but an effect related to single individual interactions in the silicon. Highly ionizing particles can directly deposit enough charge locally in the silicon to disturb the function of electronic circuits. Energetic Hadrons ( > ~20Mev) can by nuclear interactions within the component itself generate recoils that also deposits sufficient charge locally to disturb the correct function. The different SEE effects are normally characterized by an energy threshold and a sensitivity cross-section at energies well above the threshold. These studies can be performed at an associated UC Davis Laboratory.
Single event upset (SEU)
The deposited charge is sufficient to flip the value of a digital signal. Single Event Upsets normally refer to bit flips in memory circuits (RAM, Latch, flip-flop) but may also in some rare cases directly affect digital signals in logic circuits. Single event upset studies are conducted in an MNRC beamline.
Single event latchup (SEL)
Bulk CMOS technologies (not Silicon On Insulator) have parasitic bipolar transistors that can be triggered by a locally deposited charge to generate a kind of short circuit between the power supply and ground. CMOS processes are made to prevent this to occur under normal operating conditions but a local charge deposition from a traversing particle may potentially trigger this effect. Single event latchup may be limited to a small local region or may propagate to affect large parts of the chip. The large currents caused by this short circuit effect can permanently damage components if they are not externally protected against the large short circuit current and the related power dissipation.
Single event burnout (SEB)
Single event burnout refers to destructive failures of power MOSFET transistors in high power applications. For HEP applications this destructive failure mechanism is normally associated to failures in the main switching transistors of switching mode power supplies.